diff options
| author | David Daney | 2015-01-15 14:11:14 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2015-02-20 15:31:43 +0100 |
| commit | debe6a623d3cdc7f0374124830587fb8d1a04b63 (patch) | |
| tree | 002af15bade64c15267e300e9a143eb09ca82d8e /arch/mips/cavium-octeon/octeon-irq.c | |
| parent | MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX (diff) | |
| download | kernel-qcow2-linux-debe6a623d3cdc7f0374124830587fb8d1a04b63.tar.gz kernel-qcow2-linux-debe6a623d3cdc7f0374124830587fb8d1a04b63.tar.xz kernel-qcow2-linux-debe6a623d3cdc7f0374124830587fb8d1a04b63.zip | |
MIPS: OCTEON: Update octeon-model.h code for new SoCs.
Add coverage for OCTEON III models.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8942/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon/octeon-irq.c')
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-irq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 2bc4aa95944e..01bb01cf49ee 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -1210,7 +1210,7 @@ static void __init octeon_irq_init_ciu(void) if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || - OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) { chip = &octeon_irq_chip_ciu_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; |