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author | Paul Burton | 2014-04-16 12:10:57 +0200 |
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committer | Paul Burton | 2014-05-28 17:20:33 +0200 |
commit | 0155a06529d4c8425573596720829b6c578c05f2 (patch) | |
tree | 6fdb76eedde5ee9b4d4cd21a86bc6a0d7b7e298d /arch/mips/kernel/smp-cps.c | |
parent | MIPS: smp-cps: set a coherent default CCA (diff) | |
download | kernel-qcow2-linux-0155a06529d4c8425573596720829b6c578c05f2.tar.gz kernel-qcow2-linux-0155a06529d4c8425573596720829b6c578c05f2.tar.xz kernel-qcow2-linux-0155a06529d4c8425573596720829b6c578c05f2.zip |
MIPS: smp-cps: duplicate core0 CCA on secondary cores
Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from
the boot CPU. This allows overrides of the CCA using the cca= kernel
parameter to take effect on all CPUs for consistency.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/kernel/smp-cps.c')
-rw-r--r-- | arch/mips/kernel/smp-cps.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 6b96fedf0407..9e21bdd47043 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -123,9 +123,15 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) } } - /* Patch the start of mips_cps_core_entry to provide the CM base */ + /* + * Patch the start of mips_cps_core_entry to provide: + * + * v0 = CM base address + * s0 = kseg0 CCA + */ entry_code = (u32 *)&mips_cps_core_entry; UASM_i_LA(&entry_code, 3, (long)mips_cm_base); + uasm_i_addiu(&entry_code, 16, 0, cca); dma_cache_wback_inv((unsigned long)&mips_cps_core_entry, (void *)entry_code - (void *)&mips_cps_core_entry); |