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| author | Paul Burton | 2015-09-22 20:12:12 +0200 |
|---|---|---|
| committer | Ralf Baechle | 2015-11-11 08:35:01 +0100 |
| commit | 946db17349f6922a9c8a959c34ad9fb3aa238952 (patch) | |
| tree | be830ccdf2381d5840a3bda6bcee57e3658ef854 /arch/mips/kernel/smp-cps.c | |
| parent | MIPS: CPS: Early debug using an ns16550-compatible UART (diff) | |
| download | kernel-qcow2-linux-946db17349f6922a9c8a959c34ad9fb3aa238952.tar.gz kernel-qcow2-linux-946db17349f6922a9c8a959c34ad9fb3aa238952.tar.xz kernel-qcow2-linux-946db17349f6922a9c8a959c34ad9fb3aa238952.zip | |
MIPS: CPS: Read CM GCR base from cop0
Rather than patching the start of mips_cps_core_entry to provide the
base address of the CM GCRs, simply read that base address from the cop0
CMGCRBase register, converting from the physical address to an uncached
virtual address.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11203/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/smp-cps.c')
| -rw-r--r-- | arch/mips/kernel/smp-cps.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index c88937745b4e..8b967507e852 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -133,11 +133,9 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) /* * Patch the start of mips_cps_core_entry to provide: * - * v1 = CM base address * s0 = kseg0 CCA */ entry_code = (u32 *)&mips_cps_core_entry; - UASM_i_LA(&entry_code, 3, (long)mips_cm_base); uasm_i_addiu(&entry_code, 16, 0, cca); blast_dcache_range((unsigned long)&mips_cps_core_entry, (unsigned long)entry_code); |