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| author | Paul Burton | 2018-11-08 21:14:38 +0100 |
|---|---|---|
| committer | Paul Burton | 2018-11-09 19:23:19 +0100 |
| commit | 378ed6f0e3c525e3b12827e7b7fb0a078ee48a32 (patch) | |
| tree | 766bb2bdd18f7aa7fce8a9ccb428cfcad8cf2feb /arch/mips/kernel/syscall.c | |
| parent | MIPS: Allow FP support to be disabled (diff) | |
| download | kernel-qcow2-linux-378ed6f0e3c525e3b12827e7b7fb0a078ee48a32.tar.gz kernel-qcow2-linux-378ed6f0e3c525e3b12827e7b7fb0a078ee48a32.tar.xz kernel-qcow2-linux-378ed6f0e3c525e3b12827e7b7fb0a078ee48a32.zip | |
MIPS: Avoid using .set mips0 to restore ISA
We currently have 2 commonly used methods for switching ISA within
assembly code, then restoring the original ISA.
1) Using a pair of .set push & .set pop directives. For example:
.set push
.set mips32r2
<some_insn>
.set pop
2) Using .set mips0 to restore the ISA originally specified on the
command line. For example:
.set mips32r2
<some_insn>
.set mips0
Unfortunately method 2 does not work with nanoMIPS toolchains, where the
assembler rejects the .set mips0 directive like so:
Error: cannot change ISA from nanoMIPS to mips0
In preparation for supporting nanoMIPS builds, switch all instances of
method 2 in generic non-platform-specific code to use push & pop as in
method 1 instead. The .set push & .set pop is arguably cleaner anyway,
and if nothing else it's good to consistently use one method.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21037/
Cc: linux-mips@linux-mips.org
Diffstat (limited to 'arch/mips/kernel/syscall.c')
| -rw-r--r-- | arch/mips/kernel/syscall.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 69c17b549fd3..41a0db08cd37 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -106,6 +106,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__ ( + " .set push \n" " .set arch=r4000 \n" " li %[err], 0 \n" "1: ll %[old], (%[addr]) \n" @@ -122,7 +123,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) " "STR(PTR)" 1b, 4b \n" " "STR(PTR)" 2b, 4b \n" " .previous \n" - " .set mips0 \n" + " .set pop \n" : [old] "=&r" (old), [err] "=&r" (err), [tmp] "=&r" (tmp) @@ -132,6 +133,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__ ( + " .set push \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" " li %[err], 0 \n" "1: \n" @@ -150,7 +152,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) " "STR(PTR)" 1b, 5b \n" " "STR(PTR)" 2b, 5b \n" " .previous \n" - " .set mips0 \n" + " .set pop \n" : [old] "=&r" (old), [err] "=&r" (err), [tmp] "=&r" (tmp) |