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| author | Ingo Molnar | 2019-06-17 12:12:27 +0200 |
|---|---|---|
| committer | Ingo Molnar | 2019-06-17 12:12:27 +0200 |
| commit | 23da766ab1dc005860b675bf048226a11a748bf9 (patch) | |
| tree | 3f8dbfc2cf68f5da3faa3a377087b06dd8ad343d /arch/mips/kernel | |
| parent | sched/fair: Remove sgs->sum_weighted_load (diff) | |
| parent | Linux 5.2-rc5 (diff) | |
| download | kernel-qcow2-linux-23da766ab1dc005860b675bf048226a11a748bf9.tar.gz kernel-qcow2-linux-23da766ab1dc005860b675bf048226a11a748bf9.tar.xz kernel-qcow2-linux-23da766ab1dc005860b675bf048226a11a748bf9.zip | |
Merge tag 'v5.2-rc5' into sched/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/cacheinfo.c | 13 | ||||
| -rw-r--r-- | arch/mips/kernel/uprobes.c | 3 |
2 files changed, 1 insertions, 15 deletions
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c index 97d5239ca47b..e0dd66881da6 100644 --- a/arch/mips/kernel/cacheinfo.c +++ b/arch/mips/kernel/cacheinfo.c @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * MIPS cacheinfo support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/cacheinfo.h> diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c index 4aaff3b3175c..6dbe4eab0a0e 100644 --- a/arch/mips/kernel/uprobes.c +++ b/arch/mips/kernel/uprobes.c @@ -112,9 +112,6 @@ int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs) */ aup->resume_epc = regs->cp0_epc + 4; if (insn_has_delay_slot((union mips_instruction) aup->insn[0])) { - unsigned long epc; - - epc = regs->cp0_epc; __compute_return_epc_for_insn(regs, (union mips_instruction) aup->insn[0]); aup->resume_epc = regs->cp0_epc; |