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authorMarkos Chandras2014-11-26 16:43:11 +0100
committerMarkos Chandras2015-02-17 16:37:35 +0100
commit84fef630127aa90ef547ddd018d3dc47b1e79a1e (patch)
tree0331c9646f7c6b25aeb46e0fcece9046d420a1d1 /arch/mips/math-emu/cp1emu.c
parentMIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions (diff)
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MIPS: Emulate the new MIPS R6 BALC instruction
MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/math-emu/cp1emu.c')
-rw-r--r--arch/mips/math-emu/cp1emu.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 0d8407b51470..d732100c99f0 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -671,6 +671,14 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
dec_insn.next_pc_inc;
return 1;
+ case balc6_op:
+ if (!cpu_has_mips_r6)
+ break;
+ regs->regs[31] = regs->cp0_epc + 4;
+ *contpc = regs->cp0_epc + dec_insn.pc_inc +
+ dec_insn.next_pc_inc;
+
+ return 1;
#endif
case cop0_op:
case cop1_op: