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| author | Christoph Hellwig | 2018-06-15 13:08:31 +0200 |
|---|---|---|
| committer | Paul Burton | 2018-06-24 18:26:02 +0200 |
| commit | 972dc3b79f421b5ae553b1073708cbd0d4da4a91 (patch) | |
| tree | 9380232cc760aff75133abb132881db5a410512d /arch/mips/mm/cache.c | |
| parent | MIPS: remove a dead ifdef from mach-ath25/dma-coherence.h (diff) | |
| download | kernel-qcow2-linux-972dc3b79f421b5ae553b1073708cbd0d4da4a91.tar.gz kernel-qcow2-linux-972dc3b79f421b5ae553b1073708cbd0d4da4a91.tar.xz kernel-qcow2-linux-972dc3b79f421b5ae553b1073708cbd0d4da4a91.zip | |
MIPS: simplify CONFIG_DMA_NONCOHERENT ifdefs
CONFIG_DMA_MAYBE_COHERENT already selects CONFIG_DMA_NONCOHERENT, so we
can remove the extra conditions.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19529/
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-mips@linux-mips.org
Diffstat (limited to 'arch/mips/mm/cache.c')
| -rw-r--r-- | arch/mips/mm/cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 0d3c656feba0..70a523151ff3 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -56,7 +56,7 @@ EXPORT_SYMBOL_GPL(local_flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page); EXPORT_SYMBOL(flush_icache_all); -#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) +#ifdef CONFIG_DMA_NONCOHERENT /* DMA cache operations. */ void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); @@ -65,7 +65,7 @@ void (*_dma_cache_inv)(unsigned long start, unsigned long size); EXPORT_SYMBOL(_dma_cache_wback_inv); -#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ +#endif /* CONFIG_DMA_NONCOHERENT */ /* * We could optimize the case where the cache argument is not BCACHE but |