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| author | Markos Chandras | 2014-12-02 16:30:19 +0100 |
|---|---|---|
| committer | Markos Chandras | 2015-02-17 16:37:31 +0100 |
| commit | 4ee486274ec1e63f056c991e2523c32780670d08 (patch) | |
| tree | 2304dbbb0b303b67d5622cddb95abc62331a1677 /arch/mips/mm | |
| parent | MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction (diff) | |
| download | kernel-qcow2-linux-4ee486274ec1e63f056c991e2523c32780670d08.tar.gz kernel-qcow2-linux-4ee486274ec1e63f056c991e2523c32780670d08.tar.xz kernel-qcow2-linux-4ee486274ec1e63f056c991e2523c32780670d08.zip | |
MIPS: mm: c-r4k: Set the correct ISA level
The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index b806deb29e63..7ecee761ae2d 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -794,7 +794,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg) __asm__ __volatile__ ( ".set push\n\t" ".set noat\n\t" - ".set mips3\n\t" + ".set "MIPS_ISA_LEVEL"\n\t" #ifdef CONFIG_32BIT "la $at,1f\n\t" #endif |