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| author | Jayachandran C | 2013-12-21 12:22:23 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2014-01-24 22:39:48 +0100 |
| commit | 861c056953dc4354414881a5e1d382297ef4ea53 (patch) | |
| tree | 9bfdf545e1335f0dbf41bfd081bfebb72f759460 /arch/mips/netlogic/common | |
| parent | MIPS: Netlogic: XLP9XX PIC updates (diff) | |
| download | kernel-qcow2-linux-861c056953dc4354414881a5e1d382297ef4ea53.tar.gz kernel-qcow2-linux-861c056953dc4354414881a5e1d382297ef4ea53.tar.xz kernel-qcow2-linux-861c056953dc4354414881a5e1d382297ef4ea53.zip | |
MIPS: Netlogic: SYS block updates of XLP9XX
Add the SYS block registers for XLP9XX, most of them have changed.
The wakeup sequence has been updated to set the coherent mode from
the main thread rather than the woken up thread.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6280/
Diffstat (limited to 'arch/mips/netlogic/common')
| -rw-r--r-- | arch/mips/netlogic/common/reset.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S index 57eb7a141fbf..dfbf94d4df22 100644 --- a/arch/mips/netlogic/common/reset.S +++ b/arch/mips/netlogic/common/reset.S @@ -159,6 +159,13 @@ FEXPORT(nlm_reset_entry) nop 1: /* Entry point on core wakeup */ + mfc0 t0, CP0_EBASE, 0 /* processor ID */ + andi t0, 0xff00 + li t1, 0x1500 /* XLP 9xx */ + beq t0, t1, 2f /* does not need to set coherent */ + nop + + /* set bit in SYS coherent register for the core */ mfc0 t0, CP0_EBASE, 1 mfc0 t1, CP0_EBASE, 1 srl t1, 5 @@ -180,6 +187,7 @@ FEXPORT(nlm_reset_entry) lw t1, 0(t2) sync +2: /* Configure LSU on Non-0 Cores. */ xlp_config_lsu /* FALL THROUGH */ |