diff options
| author | Chris Dearman | 2007-09-19 01:58:24 +0200 |
|---|---|---|
| committer | Ralf Baechle | 2008-04-28 18:14:25 +0200 |
| commit | 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 (patch) | |
| tree | d9e9253bd30cf011d248ad3b63761a9a725e5cb0 /arch/mips/philips | |
| parent | [MIPS] Tidy up cache attributes (diff) | |
| download | kernel-qcow2-linux-351336929ccf222ae38ff0cb7a8dd5fd5c6236a0.tar.gz kernel-qcow2-linux-351336929ccf222ae38ff0cb7a8dd5fd5c6236a0.tar.xz kernel-qcow2-linux-351336929ccf222ae38ff0cb7a8dd5fd5c6236a0.zip | |
[MIPS] Allow setting of the cache attribute at run time.
Slightly tacky, but there is a precedent in the sparc archirecture code.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/philips')
| -rw-r--r-- | arch/mips/philips/pnx8550/jbs/board_setup.c | 4 | ||||
| -rw-r--r-- | arch/mips/philips/pnx8550/stb810/board_setup.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/philips/pnx8550/jbs/board_setup.c b/arch/mips/philips/pnx8550/jbs/board_setup.c index f92826e0096d..e550a3e12f65 100644 --- a/arch/mips/philips/pnx8550/jbs/board_setup.c +++ b/arch/mips/philips/pnx8550/jbs/board_setup.c @@ -53,8 +53,8 @@ void __init board_setup(void) /* clear all three cache coherency fields */ config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); + config0 |= (_page_cachable_default >> _CACHE_SHIFT) | + (CONF_CM_DEFAULT << 25) | (CONF_CM_DEFAULT << 28); write_c0_config(config0); BARRIER; diff --git a/arch/mips/philips/pnx8550/stb810/board_setup.c b/arch/mips/philips/pnx8550/stb810/board_setup.c index 345d71e53cf2..d461d7a62365 100644 --- a/arch/mips/philips/pnx8550/stb810/board_setup.c +++ b/arch/mips/philips/pnx8550/stb810/board_setup.c @@ -39,8 +39,8 @@ void __init board_setup(void) /* clear all three cache coherency fields */ config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); + config0 |= (_page_cachable_default >> _CACHE_SHIFT) | + (CONF_CM_DEFAULT << 25) | (CONF_CM_DEFAULT << 28); write_c0_config(config0); configpr = read_c0_config7(); |