diff options
| author | Atsushi Nemoto | 2008-07-25 16:01:35 +0200 |
|---|---|---|
| committer | Ralf Baechle | 2008-07-30 22:54:38 +0200 |
| commit | 455cc256eb23915100e203fb33ee143afd127954 (patch) | |
| tree | 1ad0c410fef0f7d82587347c3d3e4d4c9646dcee /arch/mips/txx9/jmr3927/irq.c | |
| parent | [MIPS] TXx9: Add some pci options (diff) | |
| download | kernel-qcow2-linux-455cc256eb23915100e203fb33ee143afd127954.tar.gz kernel-qcow2-linux-455cc256eb23915100e203fb33ee143afd127954.tar.xz kernel-qcow2-linux-455cc256eb23915100e203fb33ee143afd127954.zip | |
[MIPS] TXx9: PCI error handling
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu, 24 Jul 2008 00:25:16 +0900
Subject: [PATCH] txx9: PCI error handling
Add more control and detailed report on PCI error interrupt.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/jmr3927/irq.c')
| -rw-r--r-- | arch/mips/txx9/jmr3927/irq.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index 070c9a115e57..f3b60233e99d 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c @@ -103,22 +103,6 @@ static int jmr3927_irq_dispatch(int pending) return irq; } -#ifdef CONFIG_PCI -static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) -{ - printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); - printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", - tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); - - return IRQ_HANDLED; -} -static struct irqaction pcierr_action = { - .handler = jmr3927_pcierr_interrupt, - .mask = CPU_MASK_NONE, - .name = "PCI error", -}; -#endif - static void __init jmr3927_irq_init(void); void __init jmr3927_irq_setup(void) @@ -143,10 +127,6 @@ void __init jmr3927_irq_setup(void) /* setup IOC interrupt 1 (PCI, MODEM) */ set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); -#ifdef CONFIG_PCI - setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); -#endif - /* enable all CPU interrupt bits. */ set_c0_status(ST0_IM); /* IE bit is still 0. */ } |