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| author | Leonid Yegoshin | 2013-11-14 17:12:23 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2014-01-22 20:18:58 +0100 |
| commit | 1745c1ef88c095a99c95d13b275774d18774465d (patch) | |
| tree | 9ea07338f8852f3a6db815e8ce945023c99248ad /arch/mips | |
| parent | MIPS: mm: Move UNIQUE_ENTRYHI macro to a header file (diff) | |
| download | kernel-qcow2-linux-1745c1ef88c095a99c95d13b275774d18774465d.tar.gz kernel-qcow2-linux-1745c1ef88c095a99c95d13b275774d18774465d.tar.xz kernel-qcow2-linux-1745c1ef88c095a99c95d13b275774d18774465d.zip | |
MIPS: features: Add initial support for TLBINVF capable cores
New Aptiv cores support the TLBINVF instruction for flushing
the VTLB.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6130/
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 3 | ||||
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 | ||||
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 5 |
3 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index d445d060e346..296606b19186 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -20,6 +20,9 @@ #ifndef cpu_has_tlb #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) #endif +#ifndef cpu_has_tlbinv +#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) +#endif /* * For the moment we don't consider R6000 and R8000 so we can assume that diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index e71b49156c0c..e0a215f33d45 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -351,6 +351,7 @@ enum cpu_type_enum { #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ +#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */ /* * CPU ASE encodings diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index e2b2d2043701..a284e8cb8c28 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -286,6 +286,11 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c) && cpu_has_tlb) c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; + if (cpu_has_tlb) { + if (((config4 & MIPS_CONF4_IE) >> 29) == 2) + c->options |= MIPS_CPU_TLBINV; + } + c->kscratch_mask = (config4 >> 16) & 0xff; return config4 & MIPS_CONF_M; |