diff options
| author | Markos Chandras | 2014-04-08 13:47:13 +0200 |
|---|---|---|
| committer | Ralf Baechle | 2014-05-30 15:54:39 +0200 |
| commit | a8e897ad00d3cfd0ab9029978f0c3f8ecd6fba61 (patch) | |
| tree | ddd6a13c011c4330e9897ea354943e27c27330ed /arch/mips | |
| parent | MIPS: uasm: Add lh uam instruction (diff) | |
| download | kernel-qcow2-linux-a8e897ad00d3cfd0ab9029978f0c3f8ecd6fba61.tar.gz kernel-qcow2-linux-a8e897ad00d3cfd0ab9029978f0c3f8ecd6fba61.tar.xz kernel-qcow2-linux-a8e897ad00d3cfd0ab9029978f0c3f8ecd6fba61.zip | |
MIPS: uasm: Add mul uasm instruction
It will be used later on by bpf-jit
[ralf@linux-mips.org: Resolved conflict.]
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6736/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/uasm.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/uapi/asm/inst.h | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm-micromips.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm-mips.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/uasm.c | 3 |
5 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index a096581168df..95954ba24d31 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -134,6 +134,7 @@ Ip_u3u1u2(_lwx); Ip_u1u2u3(_mfc0); Ip_u1(_mfhi); Ip_u1u2u3(_mtc0); +Ip_u3u1u2(_mul); Ip_u3u1u2(_or); Ip_u2u1u3(_ori); Ip_u2s3u1(_pref); diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index aa37373bfd64..67933839ce6a 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -269,6 +269,7 @@ enum mm_32a_minor_op { mm_addu32_op = 0x150, mm_subu32_op = 0x1d0, mm_wsbh_op = 0x1ec, + mm_mul_op = 0x210, mm_and_op = 0x250, mm_or32_op = 0x290, mm_xor32_op = 0x310, diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c index 99d63d9825ed..9d42f1066a1f 100644 --- a/arch/mips/mm/uasm-micromips.c +++ b/arch/mips/mm/uasm-micromips.c @@ -90,6 +90,7 @@ static struct insn insn_table_MM[] = { { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS }, { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, + { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD }, { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index cb75d452ec0e..9dd15168e849 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c @@ -97,6 +97,7 @@ static struct insn insn_table[] = { { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD }, { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, + { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 6ffb60136f91..1c8bed31ec3d 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -51,7 +51,7 @@ enum opcode { insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, - insn_mfc0, insn_mfhi, insn_mtc0, insn_or, insn_ori, insn_pref, + insn_mfc0, insn_mfhi, insn_mtc0, insn_mul, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, @@ -277,6 +277,7 @@ I_u2s3u1(_lw) I_u1u2u3(_mfc0) I_u1(_mfhi) I_u1u2u3(_mtc0) +I_u3u1u2(_mul) I_u2u1u3(_ori) I_u3u1u2(_or) I_0(_rfe) |