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| author | Stafford Horne | 2017-03-23 23:13:03 +0100 |
|---|---|---|
| committer | Stafford Horne | 2017-11-03 06:01:12 +0100 |
| commit | b5f8217615bb197af33c0cc71b14783b194fed6e (patch) | |
| tree | a93d94efbb158066244235d3c9aaabad05d33f0e /arch/openrisc/Kconfig | |
| parent | openrisc: add 1 and 2 byte cmpxchg support (diff) | |
| download | kernel-qcow2-linux-b5f8217615bb197af33c0cc71b14783b194fed6e.tar.gz kernel-qcow2-linux-b5f8217615bb197af33c0cc71b14783b194fed6e.tar.xz kernel-qcow2-linux-b5f8217615bb197af33c0cc71b14783b194fed6e.zip | |
openrisc: use qspinlocks and qrwlocks
Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/Kconfig')
| -rw-r--r-- | arch/openrisc/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index 356dd67a86ea..b49acda5e8f4 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -28,6 +28,8 @@ config OPENRISC select OR1K_PIC select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 select NO_BOOTMEM + select ARCH_USE_QUEUED_SPINLOCKS + select ARCH_USE_QUEUED_RWLOCKS config CPU_BIG_ENDIAN def_bool y |