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| author | Christoph Hellwig | 2019-06-03 12:52:47 +0200 |
|---|---|---|
| committer | Christoph Hellwig | 2019-06-25 08:14:24 +0200 |
| commit | 80e61fcd23946cb222f780a49ab2eeb7ef1d3749 (patch) | |
| tree | b3b775066ec7062eccd1e0fd50d7be00475099c0 /arch/openrisc | |
| parent | arm-nommu: remove the partial DMA_ATTR_NON_CONSISTENT support (diff) | |
| download | kernel-qcow2-linux-80e61fcd23946cb222f780a49ab2eeb7ef1d3749.tar.gz kernel-qcow2-linux-80e61fcd23946cb222f780a49ab2eeb7ef1d3749.tar.xz kernel-qcow2-linux-80e61fcd23946cb222f780a49ab2eeb7ef1d3749.zip | |
arc: remove the partial DMA_ATTR_NON_CONSISTENT support
The arc DMA code supports DMA_ATTR_NON_CONSISTENT allocations, but does
not provide a cache_sync operation. This means any user of it will
never be able to actually transfer cache ownership and thus cause
coherency bugs.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Evgeniy Paltsev <paltsev@synopsys.com>
Tested-by: Evgeniy Paltsev <paltsev@synopsys.com>
Diffstat (limited to 'arch/openrisc')
0 files changed, 0 insertions, 0 deletions