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authorZhicheng Fan2012-07-10 09:52:10 +0200
committerKumar Gala2012-07-10 14:56:45 +0200
commitb5dc2986879c2a6c65a3cfede7ba6de3531a0f3e (patch)
tree0ca84b63b5e806342e000880df7426e39e6fc435 /arch/powerpc/boot/dts/fsl
parentpowerpc: select PPC_CLOCK unconditionally for FSL_SOC (diff)
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powerpc/85xx: Add ucc uart support for p1025rdb
Add device tree nodes to enable ucc uart support on P1025RDB. Signed-off-by: Zhicheng Fan <B32736@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl')
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi16
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index 4252ef85fb7a..adb82fd9057f 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -1,7 +1,7 @@
/*
* P1021/P1012 Silicon/SoC Device Tree Source (post include)
*
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -213,6 +213,20 @@
interrupt-parent = <&qeic>;
};
+ ucc@2600 {
+ cell-index = <7>;
+ reg = <0x2600 0x200>;
+ interrupts = <42>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;