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authorYangbo Lu2015-07-29 09:12:38 +0200
committerScott Wood2015-10-17 01:45:11 +0200
commit07e9117e43fc5a25787379be011e36d0980f3135 (patch)
treef838eec846a5ca0d3d668dd4dc2d0fd19580e7ea /arch/powerpc/boot/dts/p1025twr.dtsi
parentpowerpc/corenet: use the mixed mode of MPIC when enabling CPU hotplug (diff)
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powerpc/dts: Add and fix 1588 timer node for eTSEC
Add 1588 timer node in files: arch/powerpc/boot/dts/bsc9131rdb.dtsi arch/powerpc/boot/dts/bsc9132qds.dtsi arch/powerpc/boot/dts/p1010rdb.dtsi arch/powerpc/boot/dts/p1020rdb-pd.dts arch/powerpc/boot/dts/p1021rdb-pc.dtsi arch/powerpc/boot/dts/p1022ds.dtsi arch/powerpc/boot/dts/p1025twr.dtsi For P2020RDB-PC, registers' values should be calculated based on default 1588 reference clock(300MHz) not 250MHz, and fix this in file: arch/powerpc/boot/dts/p2020rdb-pc.dtsi Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts/p1025twr.dtsi')
-rw-r--r--arch/powerpc/boot/dts/p1025twr.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi b/arch/powerpc/boot/dts/p1025twr.dtsi
index 8453501c256e..08816fb474f5 100644
--- a/arch/powerpc/boot/dts/p1025twr.dtsi
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -138,6 +138,18 @@
};
};
+ ptp_clock@b0e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0xb0e00 0xb0>;
+ interrupts = <68 2 0 0 69 2 0 0>;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <2>;
+ fsl,tmr-add = <0xc0000021>;
+ fsl,tmr-fiper1 = <999999990>;
+ fsl,tmr-fiper2 = <99990>;
+ fsl,max-adj = <133333332>;
+ };
+
enet0: ethernet@b0000 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";