diff options
| author | Kumar Gala | 2011-11-07 17:22:36 +0100 |
|---|---|---|
| committer | Kumar Gala | 2011-11-24 09:01:39 +0100 |
| commit | 03f4201bd44e7d3ca7dc26b30d4251a07c77e9f2 (patch) | |
| tree | d786c935b607b77f116e6fb0446923d93b2b97f9 /arch/powerpc/boot/dts/p5020ds.dts | |
| parent | powerpc/85xx: Rework P4080DS device trees (diff) | |
| download | kernel-qcow2-linux-03f4201bd44e7d3ca7dc26b30d4251a07c77e9f2.tar.gz kernel-qcow2-linux-03f4201bd44e7d3ca7dc26b30d4251a07c77e9f2.tar.xz kernel-qcow2-linux-03f4201bd44e7d3ca7dc26b30d4251a07c77e9f2.zip | |
powerpc/85xx: Rework P5020DS device tree
Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.
Other changes include:
* Adding of MPIC timer blocks
* Dropping "fsl,p5020-IP..." from compatibles for standard blocks
* Removed mpic interrupt-parent from dcsr-epu node, just use top level
* Removed mpic interrupt-parent from sec nodes, just use top level
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/p5020ds.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/p5020ds.dts | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts index e6d40999ccd7..ceee4f50ba42 100644 --- a/arch/powerpc/boot/dts/p5020ds.dts +++ b/arch/powerpc/boot/dts/p5020ds.dts @@ -32,7 +32,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/include/ "p5020si.dtsi" +/include/ "fsl/p5020si-pre.dtsi" / { model = "fsl,P5020DS"; @@ -50,6 +50,8 @@ }; soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; spi@110000 { flash@0 { #address-cells = <1>; @@ -99,7 +101,7 @@ }; }; - localbus@ffe124000 { + lbc: localbus@ffe124000 { reg = <0xf 0xfe124000 0 0x1000>; ranges = <0 0 0xf 0xe8000000 0x08000000 2 0 0xf 0xffa00000 0x00040000 @@ -160,7 +162,7 @@ reg = <0xf 0xfe200000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; - + fsl,msi = <&msi0>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 @@ -176,6 +178,7 @@ reg = <0xf 0xfe201000 0 0x1000>; ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; + fsl,msi = <&msi1>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 @@ -191,6 +194,7 @@ reg = <0xf 0xfe202000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + fsl,msi = <&msi2>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 @@ -206,6 +210,7 @@ reg = <0xf 0xfe203000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; + fsl,msi = <&msi2>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 @@ -217,3 +222,5 @@ }; }; }; + +/include/ "fsl/p5020si-post.dtsi" |