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| author | Radim Krčmář | 2018-02-01 16:13:07 +0100 |
|---|---|---|
| committer | Radim Krčmář | 2018-02-01 16:13:07 +0100 |
| commit | d2b9b2079e23c1ab80ce1d7670d5e1994468a881 (patch) | |
| tree | bd9bfb74343da003b7bac0569d0a7f8025cbaef4 /arch/powerpc/include/asm/reg.h | |
| parent | Merge branch 'x86/hyperv' of git://git.kernel.org/pub/scm/linux/kernel/git/ti... (diff) | |
| parent | KVM: PPC: Book3S HV: Keep XIVE escalation interrupt masked unless ceded (diff) | |
| download | kernel-qcow2-linux-d2b9b2079e23c1ab80ce1d7670d5e1994468a881.tar.gz kernel-qcow2-linux-d2b9b2079e23c1ab80ce1d7670d5e1994468a881.tar.xz kernel-qcow2-linux-d2b9b2079e23c1ab80ce1d7670d5e1994468a881.zip | |
Merge tag 'kvm-ppc-next-4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
PPC KVM update for 4.16
- Allow HPT guests to run on a radix host on POWER9 v2.2 CPUs
without requiring the complex thread synchronization that earlier
CPU versions required.
- A series from Ben Herrenschmidt to improve the handling of
escalation interrupts with the XIVE interrupt controller.
- Provide for the decrementer register to be copied across on
migration.
- Various minor cleanups and bugfixes.
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b779f3ccd412..14e41b843952 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -432,8 +432,9 @@ #define SPRN_LPID 0x13F /* Logical Partition Identifier */ #endif #define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */ -#define SPRN_HMER 0x150 /* Hardware m? error recovery */ -#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */ +#define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */ +#define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */ +#define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */ #define SPRN_PCR 0x152 /* Processor compatibility register */ #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ |