diff options
| author | Michael Ellerman | 2013-04-30 22:17:04 +0200 |
|---|---|---|
| committer | Benjamin Herrenschmidt | 2013-05-02 02:37:36 +0200 |
| commit | 9353374b8e1585d5fa47a1e5c1d3e9155dd0eb7c (patch) | |
| tree | e6fdfc6f3a7aa57214fb481d965ab4378f2fbc7c /arch/powerpc/include/asm | |
| parent | powerpc: Turn on the EBB H/FSCR bits (diff) | |
| download | kernel-qcow2-linux-9353374b8e1585d5fa47a1e5c1d3e9155dd0eb7c.tar.gz kernel-qcow2-linux-9353374b8e1585d5fa47a1e5c1d3e9155dd0eb7c.tar.xz kernel-qcow2-linux-9353374b8e1585d5fa47a1e5c1d3e9155dd0eb7c.zip | |
powerpc: Context switch the new EBB SPRs
This context switches the new Event Based Branching (EBB) SPRs. The three new
SPRs are:
- Event Based Branch Handler Register (EBBHR)
- Event Based Branch Return Register (EBBRR)
- Branch Event Status and Control Register (BESCR)
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/processor.h | 3 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 0a4cc5d649e1..d7e67ca8b4a6 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -281,6 +281,9 @@ struct thread_struct { #endif #ifdef CONFIG_PPC_BOOK3S_64 unsigned long tar; + unsigned long ebbrr; + unsigned long ebbhr; + unsigned long bescr; #endif }; diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 93be5fb20394..3d17427e4fd7 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -663,6 +663,9 @@ #define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ #define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ #define SPRN_MMCRC 851 /* Core monitor mode control register */ +#define SPRN_EBBHR 804 /* Event based branch handler register */ +#define SPRN_EBBRR 805 /* Event based branch return register */ +#define SPRN_BESCR 806 /* Branch event status and control register */ #define SPRN_PMC1 787 #define SPRN_PMC2 788 |