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| author | Varun Sethi | 2012-07-09 15:01:51 +0200 |
|---|---|---|
| committer | Kumar Gala | 2012-09-12 21:57:09 +0200 |
| commit | 0778407f836d632cce90e5d9df490a7c5e6e398a (patch) | |
| tree | 1f1a6897abb055cb9230b75c8839eca10250df13 /arch/powerpc/kernel/cpu_setup_fsl_booke.S | |
| parent | powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code. (diff) | |
| download | kernel-qcow2-linux-0778407f836d632cce90e5d9df490a7c5e6e398a.tar.gz kernel-qcow2-linux-0778407f836d632cce90e5d9df490a7c5e6e398a.tar.xz kernel-qcow2-linux-0778407f836d632cce90e5d9df490a7c5e6e398a.zip | |
powerpc/booke: Separate out restore_e5500/setup_e5500 routines.
For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions.
The cpu_setup function (for the primary core) is passed the cpu_spec
pointer, which is not there in case of the cpu_restore function. Also, in
our case we will have to manipulate the CPU_FTR_EMB_HV flag on the primary
core.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_fsl_booke.S')
| -rw-r--r-- | arch/powerpc/kernel/cpu_setup_fsl_booke.S | 32 |
1 files changed, 30 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 021822daa8f6..1345e1bc748a 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -105,17 +105,45 @@ _GLOBAL(__setup_cpu_e5500) mtlr r5 blr #endif + #ifdef CONFIG_PPC_BOOK3E_64 -/* Right now, restore and setup are the same thing */ _GLOBAL(__restore_cpu_e5500) -_GLOBAL(__setup_cpu_e5500) mflr r4 bl __e500_icache_setup bl __e500_dcache_setup bl .__setup_base_ivors bl .setup_perfmon_ivor bl .setup_doorbell_ivors + /* + * We only want to touch IVOR38-41 if we're running on hardware + * that supports category E.HV. The architectural way to determine + * this is MMUCFG[LPIDSIZE]. + */ + mfspr r10,SPRN_MMUCFG + rlwinm. r10,r10,0,MMUCFG_LPIDSIZE + beq 1f bl .setup_ehv_ivors +1: mtlr r4 blr + +_GLOBAL(__setup_cpu_e5500) + mflr r5 + bl __e500_icache_setup + bl __e500_dcache_setup + bl .__setup_base_ivors + bl .setup_perfmon_ivor + bl .setup_doorbell_ivors + /* + * We only want to touch IVOR38-41 if we're running on hardware + * that supports category E.HV. The architectural way to determine + * this is MMUCFG[LPIDSIZE]. + */ + mfspr r10,SPRN_MMUCFG + rlwinm. r10,r10,0,MMUCFG_LPIDSIZE + beq 1f + bl .setup_ehv_ivors +1: + mtlr r5 + blr #endif |