diff options
| author | Michael Ellerman | 2017-10-12 13:58:54 +0200 |
|---|---|---|
| committer | Michael Ellerman | 2017-10-20 02:09:26 +0200 |
| commit | 2a3d6553cbd791da4fb624c2500b4580b3f9d72f (patch) | |
| tree | 35df7f2e78503b8facb50a7d70d6b1e22ff3c910 /arch/powerpc/kernel/idle_book3s.S | |
| parent | Revert "KVM: PPC: Book3S HV: POWER9 does not require secondary thread managem... (diff) | |
| download | kernel-qcow2-linux-2a3d6553cbd791da4fb624c2500b4580b3f9d72f.tar.gz kernel-qcow2-linux-2a3d6553cbd791da4fb624c2500b4580b3f9d72f.tar.xz kernel-qcow2-linux-2a3d6553cbd791da4fb624c2500b4580b3f9d72f.zip | |
KVM: PPC: Tie KVM_CAP_PPC_HTM to the user-visible TM feature
Currently we use CPU_FTR_TM to decide if the CPU/kernel can support
TM (Transactional Memory), and if it's true we advertise that to
Qemu (or similar) via KVM_CAP_PPC_HTM.
PPC_FEATURE2_HTM is the user-visible feature bit, which indicates that
the CPU and kernel can support TM. Currently CPU_FTR_TM and
PPC_FEATURE2_HTM always have the same value, either true or false, so
using the former for KVM_CAP_PPC_HTM is correct.
However some Power9 CPUs can operate in a mode where TM is enabled but
TM suspended state is disabled. In this mode CPU_FTR_TM is true, but
PPC_FEATURE2_HTM is false. Instead a different PPC_FEATURE2 bit is
set, to indicate that this different mode of TM is available.
It is not safe to let guests use TM as-is, when the CPU is in this
mode. So to prevent that from happening, use PPC_FEATURE2_HTM to
determine the value of KVM_CAP_PPC_HTM.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/idle_book3s.S')
0 files changed, 0 insertions, 0 deletions