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| author | Nicholas Piggin | 2017-10-24 13:44:44 +0200 |
|---|---|---|
| committer | Michael Ellerman | 2017-11-10 12:11:35 +0100 |
| commit | 1696d0fb7fcd18160c9cc92a3f2b2d68e6923dd8 (patch) | |
| tree | 1f2788739eba799f1a06e5d5ec17328b758d27c0 /arch/powerpc/kernel/setup_64.c | |
| parent | powerpc/powernv: Avoid waiting for secondary hold spinloop with OPAL (diff) | |
| download | kernel-qcow2-linux-1696d0fb7fcd18160c9cc92a3f2b2d68e6923dd8.tar.gz kernel-qcow2-linux-1696d0fb7fcd18160c9cc92a3f2b2d68e6923dd8.tar.xz kernel-qcow2-linux-1696d0fb7fcd18160c9cc92a3f2b2d68e6923dd8.zip | |
powerpc/64: Set DSCR default initially from SPR
Take the DSCR value set by firmware as the dscr_default value,
rather than zero.
POWER9 recommends DSCR default to a non-zero value.
Signed-off-by: From: Nicholas Piggin <npiggin@gmail.com>
[mpe: Make record_spr_defaults() __init]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/setup_64.c')
| -rw-r--r-- | arch/powerpc/kernel/setup_64.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index 87b4fe75fd45..8956a9856604 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -69,6 +69,8 @@ #include <asm/opal.h> #include <asm/cputhreads.h> +#include "setup.h" + #ifdef DEBUG #define DBG(fmt...) udbg_printf(fmt) #else @@ -317,6 +319,13 @@ void __init early_setup(unsigned long dt_ptr) early_init_mmu(); /* + * After firmware and early platform setup code has set things up, + * we note the SPR values for configurable control/performance + * registers, and use those as initial defaults. + */ + record_spr_defaults(); + + /* * At this point, we can let interrupts switch to virtual mode * (the MMU has been setup), so adjust the MSR in the PACA to * have IR and DR set and enable AIL if it exists |