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| author | Michael Neuling | 2012-06-25 15:33:10 +0200 |
|---|---|---|
| committer | Benjamin Herrenschmidt | 2012-07-10 11:17:55 +0200 |
| commit | c75df6f96c59beed8632e3aced5fb4faabaa6c5b (patch) | |
| tree | b21ce9394028ec4520a71d87391dad8ab29edd67 /arch/powerpc/lib/mem_64.S | |
| parent | powerpc: Modify macro ready for %r0 register change (diff) | |
| download | kernel-qcow2-linux-c75df6f96c59beed8632e3aced5fb4faabaa6c5b.tar.gz kernel-qcow2-linux-c75df6f96c59beed8632e3aced5fb4faabaa6c5b.tar.xz kernel-qcow2-linux-c75df6f96c59beed8632e3aced5fb4faabaa6c5b.zip | |
powerpc: Fix usage of register macros getting ready for %r0 change
Anything that uses a constructed instruction (ie. from ppc-opcode.h),
need to use the new R0 macro, as %r0 is not going to work.
Also convert usages of macros where we are just determining an offset
(usually for a load/store), like:
std r14,STK_REG(r14)(r1)
Can't use STK_REG(r14) as %r14 doesn't work in the STK_REG macro since
it's just calculating an offset.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/lib/mem_64.S')
| -rw-r--r-- | arch/powerpc/lib/mem_64.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/lib/mem_64.S b/arch/powerpc/lib/mem_64.S index f4fcb0bc6563..886bfc780681 100644 --- a/arch/powerpc/lib/mem_64.S +++ b/arch/powerpc/lib/mem_64.S @@ -19,7 +19,7 @@ _GLOBAL(memset) rlwimi r4,r4,16,0,15 cmplw cr1,r5,r0 /* do we get that far? */ rldimi r4,r4,32,0 - PPC_MTOCRF(1,r0) + PPC_MTOCRF(1,R0) mr r6,r3 blt cr1,8f beq+ 3f /* if already 8-byte aligned */ @@ -49,7 +49,7 @@ _GLOBAL(memset) bdnz 4b 5: srwi. r0,r5,3 clrlwi r5,r5,29 - PPC_MTOCRF(1,r0) + PPC_MTOCRF(1,R0) beq 8f bf 29,6f std r4,0(r6) @@ -65,7 +65,7 @@ _GLOBAL(memset) std r4,0(r6) addi r6,r6,8 8: cmpwi r5,0 - PPC_MTOCRF(1,r5) + PPC_MTOCRF(1,R5) beqlr+ bf 29,9f stw r4,0(r6) |