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| author | Aneesh Kumar K.V | 2016-04-29 15:26:23 +0200 |
|---|---|---|
| committer | Michael Ellerman | 2016-05-11 13:53:54 +0200 |
| commit | 5ed7ecd08a0807d6d616c3d958402f9c723bb048 (patch) | |
| tree | 416bd1a8321d42861a301e10eecd0f37902fd1d6 /arch/powerpc/mm/hash_utils_64.c | |
| parent | powerpc/radix: Update MMU cache (diff) | |
| download | kernel-qcow2-linux-5ed7ecd08a0807d6d616c3d958402f9c723bb048.tar.gz kernel-qcow2-linux-5ed7ecd08a0807d6d616c3d958402f9c723bb048.tar.xz kernel-qcow2-linux-5ed7ecd08a0807d6d616c3d958402f9c723bb048.zip | |
powerpc/mm: pte_frag abstraction
In this patch we make the number of pte fragments per level 4 page table
page a variable. Radix level 4 table size is 256 bytes and hence we can
have 256 fragments per level 4 page. We don't update the fragment count
in this patch. We need to do performance measurements to find the right
value for fragment count.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm/hash_utils_64.c')
| -rw-r--r-- | arch/powerpc/mm/hash_utils_64.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 68aee435ea97..262082e51db1 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -873,6 +873,9 @@ void __init hash__early_init_mmu(void) /* * initialize page table size */ + __pte_frag_nr = H_PTE_FRAG_NR; + __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; + __pte_index_size = H_PTE_INDEX_SIZE; __pmd_index_size = H_PMD_INDEX_SIZE; __pud_index_size = H_PUD_INDEX_SIZE; |