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| author | Kumar Gala | 2010-10-08 09:13:25 +0200 |
|---|---|---|
| committer | Kumar Gala | 2010-10-14 07:55:09 +0200 |
| commit | 988cf86d4f0da4150e808300c145ba87c0aad02f (patch) | |
| tree | b6b1c4ce5e06722bacff5b1fc852ae9de4f54530 /arch/powerpc/mm/tlb_nohash_low.S | |
| parent | powerpc/fsl-booke: Add support for FSL 64-bit e5500 core (diff) | |
| download | kernel-qcow2-linux-988cf86d4f0da4150e808300c145ba87c0aad02f.tar.gz kernel-qcow2-linux-988cf86d4f0da4150e808300c145ba87c0aad02f.tar.xz kernel-qcow2-linux-988cf86d4f0da4150e808300c145ba87c0aad02f.zip | |
powerpc/fsl-booke: Add support for FSL Arch v1.0 MMU in setup_page_sizes
Update setup_page_sizes() to support for a MMU v1.0 FSL style MMU
implementation. In such a processor, we don't have TLB0PS or EPTCFG
registers (and access to these registers may cause exceptions). We need
to parse the older format of TLBnCFG for page size support. Additionaly,
assume since we are an FSL implementation that we have 2 TLB arrays and
the second array contains the variable size pages.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/tlb_nohash_low.S')
0 files changed, 0 insertions, 0 deletions