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| author | Benjamin Herrenschmidt | 2009-07-24 01:15:24 +0200 |
|---|---|---|
| committer | Benjamin Herrenschmidt | 2009-08-20 02:12:41 +0200 |
| commit | d4e167da4cb60910f6ac305aee03714937f70b71 (patch) | |
| tree | 44a0faf402dd91024544b3450033b80524b25799 /arch/powerpc/mm/tlb_nohash_low.S | |
| parent | powerpc: Modify some ppc_asm.h macros to accomodate 64-bits Book3E (diff) | |
| download | kernel-qcow2-linux-d4e167da4cb60910f6ac305aee03714937f70b71.tar.gz kernel-qcow2-linux-d4e167da4cb60910f6ac305aee03714937f70b71.tar.xz kernel-qcow2-linux-d4e167da4cb60910f6ac305aee03714937f70b71.zip | |
powerpc/mm: Make low level TLB flush ops on BookE take additional args
We need to pass down whether the page is direct or indirect and we'll
need to pass the page size to _tlbil_va and _tlbivax_bcast
We also add a new low level _tlbil_pid_noind() which does a TLB flush
by PID but avoids flushing indirect entries if possible
This implements those new prototypes but defines them with inlines
or macros so that no additional arguments are actually passed on current
processors.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/tlb_nohash_low.S')
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash_low.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index 3037911279b1..c7d89a0adba2 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -39,7 +39,7 @@ /* * 40x implementation needs only tlbil_va */ -_GLOBAL(_tlbil_va) +_GLOBAL(__tlbil_va) /* We run the search with interrupts disabled because we have to change * the PID and I don't want to preempt when that happens. */ @@ -71,7 +71,7 @@ _GLOBAL(_tlbil_va) * 440 implementation uses tlbsx/we for tlbil_va and a full sweep * of the TLB for everything else. */ -_GLOBAL(_tlbil_va) +_GLOBAL(__tlbil_va) mfspr r5,SPRN_MMUCR rlwimi r5,r4,0,24,31 /* Set TID */ @@ -170,7 +170,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX) * Flush MMU TLB for a particular address, but only on the local processor * (no broadcast) */ -_GLOBAL(_tlbil_va) +_GLOBAL(__tlbil_va) mfmsr r10 wrteei 0 slwi r4,r4,16 |