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| author | Catalin Udma | 2013-06-05 22:22:08 +0200 |
|---|---|---|
| committer | Scott Wood | 2013-08-08 01:38:03 +0200 |
| commit | 96c3c9e78f7fe45303985cce13ce26e35afd01ba (patch) | |
| tree | 96f0e95f0472e909dde39b3e1afe505a53398d2e /arch/powerpc/perf | |
| parent | powerpc/perf: correct typos in counter enumeration (diff) | |
| download | kernel-qcow2-linux-96c3c9e78f7fe45303985cce13ce26e35afd01ba.tar.gz kernel-qcow2-linux-96c3c9e78f7fe45303985cce13ce26e35afd01ba.tar.xz kernel-qcow2-linux-96c3c9e78f7fe45303985cce13ce26e35afd01ba.zip | |
powerpc/perf: increase the perf HW events to 6
This change is required after the e6500 perf support has been added.
There are 6 counters in e6500 core instead of 4 in e500 core and
the MAX_HWEVENTS counter should be changed accordingly from 4 to 6.
Added also runtime check for counters overflow.
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/perf')
| -rw-r--r-- | arch/powerpc/perf/core-fsl-emb.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c index 106c53354675..0b13f74f5fb3 100644 --- a/arch/powerpc/perf/core-fsl-emb.c +++ b/arch/powerpc/perf/core-fsl-emb.c @@ -462,6 +462,12 @@ static int fsl_emb_pmu_event_init(struct perf_event *event) int num_restricted; int i; + if (ppmu->n_counter > MAX_HWEVENTS) { + WARN(1, "No. of perf counters (%d) is higher than max array size(%d)\n", + ppmu->n_counter, MAX_HWEVENTS); + ppmu->n_counter = MAX_HWEVENTS; + } + switch (event->attr.type) { case PERF_TYPE_HARDWARE: ev = event->attr.config; |