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| author | Arnd Bergmann | 2008-11-28 10:51:24 +0100 |
|---|---|---|
| committer | Paul Mackerras | 2008-11-30 23:40:18 +0100 |
| commit | 960cedb4e3eedec6394f224fc832c7a23f35a799 (patch) | |
| tree | 09c0a325ac79ff81d4968ec6f4e22d88efbcfcb5 /arch/powerpc/platforms/cell/smp.c | |
| parent | powerpc/mpic: Don't reset affinity for secondary MPIC on boot (diff) | |
| download | kernel-qcow2-linux-960cedb4e3eedec6394f224fc832c7a23f35a799.tar.gz kernel-qcow2-linux-960cedb4e3eedec6394f224fc832c7a23f35a799.tar.xz kernel-qcow2-linux-960cedb4e3eedec6394f224fc832c7a23f35a799.zip | |
powerpc/cell: Fix GDB watchpoints, again
An earlier patch from Jens Osterkamp attempted to fix GDB
watchpoints by enabling the DABRX register at boot time.
Unfortunately, this did not work on SMP setups, where
secondary CPUs were still using the power-on DABRX value.
This introduces the same change for secondary CPUs on cell
as well.
Reported-by: Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
Tested-by: Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/cell/smp.c')
| -rw-r--r-- | arch/powerpc/platforms/cell/smp.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c index c0d86e1f56ea..9046803c8276 100644 --- a/arch/powerpc/platforms/cell/smp.c +++ b/arch/powerpc/platforms/cell/smp.c @@ -129,10 +129,15 @@ static int __init smp_iic_probe(void) return cpus_weight(cpu_possible_map); } -static void __devinit smp_iic_setup_cpu(int cpu) +static void __devinit smp_cell_setup_cpu(int cpu) { if (cpu != boot_cpuid) iic_setup_cpu(); + + /* + * change default DABRX to allow user watchpoints + */ + mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); } static DEFINE_SPINLOCK(timebase_lock); @@ -192,7 +197,7 @@ static struct smp_ops_t bpa_iic_smp_ops = { .message_pass = smp_iic_message_pass, .probe = smp_iic_probe, .kick_cpu = smp_cell_kick_cpu, - .setup_cpu = smp_iic_setup_cpu, + .setup_cpu = smp_cell_setup_cpu, .cpu_bootable = smp_cell_cpu_bootable, }; |