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| author | Gautham R. Shenoy | 2017-03-22 16:04:14 +0100 |
|---|---|---|
| committer | Michael Ellerman | 2017-04-11 00:45:09 +0200 |
| commit | a7cd88da97040513e17cd77ae3e57764e854bae4 (patch) | |
| tree | fdc2d2a70872488ac399dcccca485722791ec528 /arch/powerpc/platforms/powernv/idle.c | |
| parent | powerpc/hugetlb: Add ABI defines for supported HugeTLB page sizes (diff) | |
| download | kernel-qcow2-linux-a7cd88da97040513e17cd77ae3e57764e854bae4.tar.gz kernel-qcow2-linux-a7cd88da97040513e17cd77ae3e57764e854bae4.tar.xz kernel-qcow2-linux-a7cd88da97040513e17cd77ae3e57764e854bae4.zip | |
powerpc/powernv: Move CPU-Offline idle state invocation from smp.c to idle.c
Move the piece of code in powernv/smp.c::pnv_smp_cpu_kill_self() which
transitions the CPU to the deepest available platform idle state to a
new function named pnv_cpu_offline() in powernv/idle.c. The rationale
behind this code movement is that the data required to determine the
deepest available platform state resides in powernv/idle.c.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/platforms/powernv/idle.c')
| -rw-r--r-- | arch/powerpc/platforms/powernv/idle.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c index 4ee837e6391a..419edffec516 100644 --- a/arch/powerpc/platforms/powernv/idle.c +++ b/arch/powerpc/platforms/powernv/idle.c @@ -266,6 +266,31 @@ u64 pnv_deepest_stop_psscr_val; u64 pnv_deepest_stop_psscr_mask; /* + * pnv_cpu_offline: A function that puts the CPU into the deepest + * available platform idle state on a CPU-Offline. + */ +unsigned long pnv_cpu_offline(unsigned int cpu) +{ + unsigned long srr1; + + u32 idle_states = pnv_get_supported_cpuidle_states(); + + if (cpu_has_feature(CPU_FTR_ARCH_300)) { + srr1 = power9_idle_stop(pnv_deepest_stop_psscr_val, + pnv_deepest_stop_psscr_mask); + } else if (idle_states & OPAL_PM_WINKLE_ENABLED) { + srr1 = power7_winkle(); + } else if ((idle_states & OPAL_PM_SLEEP_ENABLED) || + (idle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { + srr1 = power7_sleep(); + } else { + srr1 = power7_nap(1); + } + + return srr1; +} + +/* * Power ISA 3.0 idle initialization. * * POWER ISA 3.0 defines a new SPR Processor stop Status and Control |