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authorYijing Wang2013-09-05 09:55:26 +0200
committerBjorn Helgaas2013-09-24 01:30:03 +0200
commitad4d35f865408a494f0a4c02b1c7ebd3f80f5dbf (patch)
tree3fc6033c5ea9a39a385505101580f4b12742460b /arch/powerpc/sysdev/fsl_pci.c
parent[SCSI] bfa: Use pcie_set()/get_readrq() to simplify code (diff)
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[SCSI] csiostor: Use pcie_capability_clear_and_set_word() to simplify code
pci_is_pcie() and pcie_capability_clear_and_set_word() make it trivial to set the PCIe Completion Timeout, so just fold the csio_set_pcie_completion_timeout() function into its caller. [bhelgaas: changelog, fold csio_set_pcie_completion_timeout() into caller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@huawei.com> Cc: "James E.J. Bottomley" <JBottomley@parallels.com> Cc: Naresh Kumar Inna <naresh@chelsio.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jesper Juhl <jj@chaosbits.net>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.c')
0 files changed, 0 insertions, 0 deletions