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| author | Kumar Gala | 2005-08-31 06:54:47 +0200 |
|---|---|---|
| committer | Linus Torvalds | 2005-09-01 19:52:29 +0200 |
| commit | 80ac2912f846c01d702774bb6aa7100ec71e88b9 (patch) | |
| tree | a43d483cf144eb0f770a6e2e8ac9f721965a7fa9 /arch/ppc/kernel/cpu_setup_6xx.S | |
| parent | [PATCH] Fix PCI ROM mapping (diff) | |
| download | kernel-qcow2-linux-80ac2912f846c01d702774bb6aa7100ec71e88b9.tar.gz kernel-qcow2-linux-80ac2912f846c01d702774bb6aa7100ec71e88b9.tar.xz kernel-qcow2-linux-80ac2912f846c01d702774bb6aa7100ec71e88b9.zip | |
[PATCH] ppc: L2 cache prefetch fixes on 745x
We run into problems if we blindly enable L2 prefetching without
checking that the L2 cache is actually enabled. Additionaly, if we
disable the L2 cache we need to ensure that we disable L2 prefetching.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/kernel/cpu_setup_6xx.S')
| -rw-r--r-- | arch/ppc/kernel/cpu_setup_6xx.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S index 468721d9ebd2..3fb1fb619d2c 100644 --- a/arch/ppc/kernel/cpu_setup_6xx.S +++ b/arch/ppc/kernel/cpu_setup_6xx.S @@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) sync isync - /* Enable L2 HW prefetch + /* Enable L2 HW prefetch, if L2 is enabled */ + mfspr r3,SPRN_L2CR + andis. r3,r3,L2CR_L2E@h + beqlr mfspr r3,SPRN_MSSCR0 ori r3,r3,3 sync |