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author | David S. Miller | 2019-06-18 04:48:13 +0200 |
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committer | David S. Miller | 2019-06-18 05:20:36 +0200 |
commit | 13091aa30535b719e269f20a7bc34002bf5afae5 (patch) | |
tree | bd17956c3ce606a119fadbd43bfa1c0c10006984 /arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | |
parent | Merge branch 'UDP-GSO-audit-tests' (diff) | |
parent | Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs (diff) | |
download | kernel-qcow2-linux-13091aa30535b719e269f20a7bc34002bf5afae5.tar.gz kernel-qcow2-linux-13091aa30535b719e269f20a7bc34002bf5afae5.tar.xz kernel-qcow2-linux-13091aa30535b719e269f20a7bc34002bf5afae5.zip |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Honestly all the conflicts were simple overlapping changes,
nothing really interesting to report.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts')
-rw-r--r-- | arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts new file mode 100644 index 000000000000..4da88707e28f --- /dev/null +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; +}; + +&qspi0 { + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; |