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| author | Linus Torvalds | 2019-08-17 19:36:47 +0200 |
|---|---|---|
| committer | Linus Torvalds | 2019-08-17 19:36:47 +0200 |
| commit | 2f478b60118f48bf66eaddcca0d23e80f87a682d (patch) | |
| tree | 9a4e6341f103e0e758f58b9db3e3d3a325145737 /arch/riscv/configs/defconfig | |
| parent | Merge tag 'xtensa-20190816' of git://github.com/jcmvbkbc/linux-xtensa (diff) | |
| parent | riscv: Make __fstate_clean() work correctly. (diff) | |
| download | kernel-qcow2-linux-2f478b60118f48bf66eaddcca0d23e80f87a682d.tar.gz kernel-qcow2-linux-2f478b60118f48bf66eaddcca0d23e80f87a682d.tar.xz kernel-qcow2-linux-2f478b60118f48bf66eaddcca0d23e80f87a682d.zip | |
Merge tag 'riscv/for-v5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley:
- Two patches to fix significant bugs in floating point register
context handling
- A minor fix in RISC-V flush_tlb_page(), to supply a valid end address
to flush_tlb_range()
- Two minor defconfig additions: to build the virtio hwrng driver by
default (for QEMU targets), and to partially synchronize the 32-bit
defconfig with the 64-bit defconfig
* tag 'riscv/for-v5.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Make __fstate_clean() work correctly.
riscv: Correct the initialized flow of FP register
riscv: defconfig: Update the defconfig
riscv: rv32_defconfig: Update the defconfig
riscv: fix flush_tlb_range() end address for flush_tlb_page()
Diffstat (limited to 'arch/riscv/configs/defconfig')
| -rw-r--r-- | arch/riscv/configs/defconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 93205c0bf71d..3efff552a261 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -54,6 +54,8 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y CONFIG_SPI=y CONFIG_SPI_SIFIVE=y # CONFIG_PTP_1588_CLOCK is not set |