diff options
| author | Vincent Chen | 2019-03-05 04:23:34 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-17 05:42:12 +0200 |
| commit | ee72e0e70cf7c846a4e0b6160f771da8f68571dc (patch) | |
| tree | d08fef2622f07eb5df0825c147348fe149c696f3 /arch/riscv/include | |
| parent | riscv: support trap-based WARN() (diff) | |
| download | kernel-qcow2-linux-ee72e0e70cf7c846a4e0b6160f771da8f68571dc.tar.gz kernel-qcow2-linux-ee72e0e70cf7c846a4e0b6160f771da8f68571dc.tar.xz kernel-qcow2-linux-ee72e0e70cf7c846a4e0b6160f771da8f68571dc.zip | |
riscv: Add the support for c.ebreak check in is_valid_bugaddr()
The macro __BUG_INSN currently is defined as the "ebreak" opcode.
The is_valid_bugaddr() function compares the instruction pointed to by
$sepc with macro __BUG_INSN to check whether the current trap exception
is caused by an "ebreak" instruction. However, this check flow is possibly
erroneous because if C extension is supported, the expected trap
instruction "ebreak" is possibly translated to "c.ebreak" by the assembler.
Therefore, it requires a mechanism to distinguish the length of the
instruction in $spec and compare it to the correct trap instruction.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/bug.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/bug.h b/arch/riscv/include/asm/bug.h index 4d906d82277b..52a1fbdeab3b 100644 --- a/arch/riscv/include/asm/bug.h +++ b/arch/riscv/include/asm/bug.h @@ -21,7 +21,12 @@ #include <asm/asm.h> #ifdef CONFIG_GENERIC_BUG -#define __BUG_INSN _AC(0x00100073, UL) /* ebreak */ +#define __INSN_LENGTH_MASK _UL(0x3) +#define __INSN_LENGTH_32 _UL(0x3) +#define __COMPRESSED_INSN_MASK _UL(0xffff) + +#define __BUG_INSN_32 _UL(0x00100073) /* ebreak */ +#define __BUG_INSN_16 _UL(0x9002) /* c.ebreak */ #ifndef __ASSEMBLY__ typedef u32 bug_insn_t; |