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| author | Chris Metcalf | 2013-09-03 20:41:36 +0200 |
|---|---|---|
| committer | Chris Metcalf | 2013-09-03 20:47:34 +0200 |
| commit | acbde1db294932623aad15dd8cc6e37b28340f26 (patch) | |
| tree | 735ae530754f49ecfb006765463defdeea1167cd /arch/tile/kernel/intvec_32.S | |
| parent | tile: don't assume user privilege is zero (diff) | |
| download | kernel-qcow2-linux-acbde1db294932623aad15dd8cc6e37b28340f26.tar.gz kernel-qcow2-linux-acbde1db294932623aad15dd8cc6e37b28340f26.tar.xz kernel-qcow2-linux-acbde1db294932623aad15dd8cc6e37b28340f26.zip | |
tile: parameterize VA and PA space more cleanly
The existing code relied on the hardware definition (<arch/chip.h>)
to specify how much VA and PA space was available. It's convenient
to allow customizing this for some configurations, so provide symbols
MAX_PA_WIDTH and MAX_VA_WIDTH in <asm/page.h> that can be modified
if desired.
Additionally, move away from the MEM_XX_INTRPT nomenclature to
define the start of various regions within the VA space. In fact
the cleaner symbol is, for example, MEM_SV_START, to indicate the
start of the area used for supervisor code; the actual address of the
interrupt vectors is not as important, and can be changed if desired.
As part of this change, convert from "intrpt1" nomenclature (which
built in the old privilege-level 1 model) to a simple "intrpt".
Also strip out some tilepro-specific code supporting modifying the
PL the kernel could run at, since we don't actually support using
different PLs in tilepro, only tilegx.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel/intvec_32.S')
| -rw-r--r-- | arch/tile/kernel/intvec_32.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S index f3d26f48e659..f084f1c7afde 100644 --- a/arch/tile/kernel/intvec_32.S +++ b/arch/tile/kernel/intvec_32.S @@ -353,7 +353,7 @@ intvec_\vecname: #ifdef __COLLECT_LINKER_FEEDBACK__ .pushsection .text.intvec_feedback,"ax" .org (\vecnum << 5) - FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8) + FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt, 1 << 8) jrp lr .popsection #endif @@ -1890,8 +1890,8 @@ int_unalign: push_extra_callee_saves r0 j do_trap -/* Include .intrpt1 array of interrupt vectors */ - .section ".intrpt1", "ax" +/* Include .intrpt array of interrupt vectors */ + .section ".intrpt", "ax" #define op_handle_perf_interrupt bad_intr #define op_handle_aux_perf_interrupt bad_intr |