diff options
| author | Jiri Olsa | 2019-05-12 17:55:15 +0200 |
|---|---|---|
| committer | Ingo Molnar | 2019-06-03 11:58:24 +0200 |
| commit | 1f157286829c78c0bd8e495951a5c098d88e3d1a (patch) | |
| tree | 3ba602afd97fce1dc0dc6ab049eb40fb693872b7 /arch/x86/events | |
| parent | perf/x86: Add is_visible attribute_group callback for base events (diff) | |
| download | kernel-qcow2-linux-1f157286829c78c0bd8e495951a5c098d88e3d1a.tar.gz kernel-qcow2-linux-1f157286829c78c0bd8e495951a5c098d88e3d1a.tar.xz kernel-qcow2-linux-1f157286829c78c0bd8e495951a5c098d88e3d1a.zip | |
perf/x86: Use update attribute groups for caps
Using the new pmu::update_attrs attribute group for
"caps" directory.
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20190512155518.21468-7-jolsa@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/core.c | 8 | ||||
| -rw-r--r-- | arch/x86/events/intel/core.c | 25 | ||||
| -rw-r--r-- | arch/x86/events/perf_event.h | 1 |
3 files changed, 20 insertions, 14 deletions
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index b831091d4c10..dd0996ba75c3 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1821,14 +1821,6 @@ static int __init init_hw_perf_events(void) x86_pmu_format_group.attrs = x86_pmu.format_attrs; - if (x86_pmu.caps_attrs) { - struct attribute **tmp; - - tmp = merge_attr(x86_pmu_caps_group.attrs, x86_pmu.caps_attrs); - if (!WARN_ON(!tmp)) - x86_pmu_caps_group.attrs = tmp; - } - if (!x86_pmu.events_sysfs_show) x86_pmu_events_group.attrs = &empty_attrs; diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 600e87055ba9..d4002e71a0b8 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4411,6 +4411,12 @@ pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) return x86_pmu.pebs ? attr->mode : 0; } +static umode_t +lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) +{ + return x86_pmu.lbr_nr ? attr->mode : 0; +} + static struct attribute_group group_events_td = { .name = "events", }; @@ -4425,10 +4431,23 @@ static struct attribute_group group_events_tsx = { .is_visible = tsx_is_visible, }; +static struct attribute_group group_caps_gen = { + .name = "caps", + .attrs = intel_pmu_caps_attrs, +}; + +static struct attribute_group group_caps_lbr = { + .name = "caps", + .attrs = lbr_attrs, + .is_visible = lbr_is_visible, +}; + static const struct attribute_group *attr_update[] = { &group_events_td, &group_events_mem, &group_events_tsx, + &group_caps_gen, + &group_caps_lbr, NULL, }; @@ -5055,12 +5074,8 @@ __init int intel_pmu_init(void) x86_pmu.lbr_nr = 0; } - x86_pmu.caps_attrs = intel_pmu_caps_attrs; - - if (x86_pmu.lbr_nr) { - x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs); + if (x86_pmu.lbr_nr) pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); - } /* * Access extra MSR may cause #GP under certain circumstances. diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 629b313d8b8b..1da9b6f0b279 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -631,7 +631,6 @@ struct x86_pmu { int attr_rdpmc_broken; int attr_rdpmc; struct attribute **format_attrs; - struct attribute **caps_attrs; ssize_t (*events_sysfs_show)(char *page, u64 config); const struct attribute_group **attr_update; |