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| author | Suresh Siddha | 2008-07-29 19:29:20 +0200 |
|---|---|---|
| committer | Ingo Molnar | 2008-07-30 19:49:24 +0200 |
| commit | b359e8a434cc3d09847010fc4aeccf48d69740e4 (patch) | |
| tree | 8911c299dc1768c78d5452a1e7e0efd2fc8d5abb /arch/x86/ia32/ia32_signal.c | |
| parent | x86, xsave: enable xsave/xrstor on cpus with xsave support (diff) | |
| download | kernel-qcow2-linux-b359e8a434cc3d09847010fc4aeccf48d69740e4.tar.gz kernel-qcow2-linux-b359e8a434cc3d09847010fc4aeccf48d69740e4.tar.xz kernel-qcow2-linux-b359e8a434cc3d09847010fc4aeccf48d69740e4.zip | |
x86, xsave: context switch support using xsave/xrstor
Uses xsave/xrstor (instead of traditional fxsave/fxrstor) in context switch
when available.
Introduces TS_XSAVE flag, which determine the need to use xsave/xrstor
instructions during context switch instead of the legacy fxsave/fxrstor
instructions. Thread-synchronous status word is already in L1 cache during
this code patch and thus minimizes the performance penality compared to
(cpu_has_xsave) checks.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/ia32/ia32_signal.c')
0 files changed, 0 insertions, 0 deletions