diff options
| author | Tony Luck | 2017-04-03 23:44:16 +0200 |
|---|---|---|
| committer | Thomas Gleixner | 2017-04-05 17:22:31 +0200 |
| commit | c4026b7b95a4b852e404afa2cd7720866159d118 (patch) | |
| tree | 60089e1fd1ad26b24d915b9e1d82b06092e69ee4 /arch/x86/include/asm/intel_rdt.h | |
| parent | x86/cpu: Drop wp_works_ok member of struct cpuinfo_x86 (diff) | |
| download | kernel-qcow2-linux-c4026b7b95a4b852e404afa2cd7720866159d118.tar.gz kernel-qcow2-linux-c4026b7b95a4b852e404afa2cd7720866159d118.tar.xz kernel-qcow2-linux-c4026b7b95a4b852e404afa2cd7720866159d118.zip | |
x86/intel_rdt: Implement "update" mode when writing schemata file
The schemata file can have multiple lines and it is cumbersome to update
all lines.
Remove code that requires that the user provides values for every resource
(in the right order). If the user provides values for just a few
resources, update them and leave the rest unchanged.
Side benefit: we now check which values were updated and only send IPIs to
cpus that actually have updates.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Tested-by: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
Cc: ravi.v.shankar@intel.com
Cc: fenghua.yu@intel.com
Cc: peterz@infradead.org
Cc: vikas.shivappa@intel.com
Cc: h.peter.anvin@intel.com
Link: http://lkml.kernel.org/r/1491255857-17213-3-git-send-email-vikas.shivappa@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/asm/intel_rdt.h')
| -rw-r--r-- | arch/x86/include/asm/intel_rdt.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h index 0d64397cee58..d7705270c401 100644 --- a/arch/x86/include/asm/intel_rdt.h +++ b/arch/x86/include/asm/intel_rdt.h @@ -76,10 +76,7 @@ struct rftype { * @min_cbm_bits: Minimum number of consecutive bits to be set * in a cache bit mask * @domains: All domains for this resource - * @num_domains: Number of domains active * @msr_base: Base MSR address for CBMs - * @tmp_cbms: Scratch space when updating schemata - * @num_tmp_cbms: Number of CBMs in tmp_cbms * @cache_level: Which cache level defines scope of this domain * @cbm_idx_multi: Multiplier of CBM index * @cbm_idx_offset: Offset of CBM index. CBM index is computed by: @@ -94,10 +91,7 @@ struct rdt_resource { int min_cbm_bits; u32 max_cbm; struct list_head domains; - int num_domains; int msr_base; - u32 *tmp_cbms; - int num_tmp_cbms; int cache_level; int cbm_idx_multi; int cbm_idx_offset; @@ -109,12 +103,16 @@ struct rdt_resource { * @id: unique id for this instance * @cpu_mask: which cpus share this resource * @cbm: array of cache bit masks (indexed by CLOSID) + * @new_cbm: new cbm value to be loaded + * @have_new_cbm: did user provide new_cbm for this domain */ struct rdt_domain { struct list_head list; int id; struct cpumask cpu_mask; u32 *cbm; + u32 new_cbm; + bool have_new_cbm; }; /** |