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| author | Tony Luck | 2016-11-18 18:48:36 +0100 |
|---|---|---|
| committer | Thomas Gleixner | 2016-11-23 16:51:52 +0100 |
| commit | 3f5a7896a5096fd50030a04d4c3f28a7441e30a5 (patch) | |
| tree | 3ec4ee771f874daac8b1519b117f156049a29f89 /arch/x86/include/asm/msr-index.h | |
| parent | x86/mce/AMD: Add system physical address translation for AMD Fam17h (diff) | |
| download | kernel-qcow2-linux-3f5a7896a5096fd50030a04d4c3f28a7441e30a5.tar.gz kernel-qcow2-linux-3f5a7896a5096fd50030a04d4c3f28a7441e30a5.tar.xz kernel-qcow2-linux-3f5a7896a5096fd50030a04d4c3f28a7441e30a5.zip | |
x86/mce: Include the PPIN in MCE records when available
Intel Xeons from Ivy Bridge onwards support a processor identification
number set in the factory. To the user this is a handy unique number to
identify a particular CPU. Intel can decode this to the fab/production
run to track errors. On systems that have it, include it in the machine
check record. I'm told that this would be helpful for users that run
large data centers with multi-socket servers to keep track of which CPUs
are seeing errors.
Boris:
* Add some clarifying comments and spacing.
* Mask out [63:2] in the disabled-but-not-locked case
* Call the MSR variable "val" for more readability.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/20161123114855.njguoaygp3qnbkia@pd.tnic
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 78f3760ca1f2..710273c617b8 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -37,6 +37,10 @@ #define EFER_FFXSR (1<<_EFER_FFXSR) /* Intel MSRs. Some also available on other CPUs */ + +#define MSR_PPIN_CTL 0x0000004e +#define MSR_PPIN 0x0000004f + #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd |