diff options
| author | Juergen Gross | 2014-11-03 14:02:03 +0100 |
|---|---|---|
| committer | Thomas Gleixner | 2014-11-16 11:04:26 +0100 |
| commit | bd809af16e3ab1f8d55b3e2928c47c67e2a865d2 (patch) | |
| tree | 8ac5084b758cc1af91737e070d281f041df470c0 /arch/x86/include/asm/pgtable_types.h | |
| parent | x86: Respect PAT bit when copying pte values between large and normal pages (diff) | |
| download | kernel-qcow2-linux-bd809af16e3ab1f8d55b3e2928c47c67e2a865d2.tar.gz kernel-qcow2-linux-bd809af16e3ab1f8d55b3e2928c47c67e2a865d2.tar.xz kernel-qcow2-linux-bd809af16e3ab1f8d55b3e2928c47c67e2a865d2.zip | |
x86: Enable PAT to use cache mode translation tables
Update the translation tables from cache mode to pgprot values
according to the PAT settings. This enables changing the cache
attributes of a PAT index in just one place without having to change
at the users side.
With this change it is possible to use the same kernel with different
PAT configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Toshi Kani <toshi.kani@hp.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stefan.bader@canonical.com
Cc: xen-devel@lists.xensource.com
Cc: ville.syrjala@linux.intel.com
Cc: david.vrabel@citrix.com
Cc: jbeulich@suse.com
Cc: plagnioj@jcrosoft.com
Cc: tomi.valkeinen@ti.com
Cc: bhelgaas@google.com
Link: http://lkml.kernel.org/r/1415019724-4317-18-git-send-email-jgross@suse.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/asm/pgtable_types.h')
| -rw-r--r-- | arch/x86/include/asm/pgtable_types.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 6d5f6d154215..af447f95e3be 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -351,6 +351,10 @@ extern uint8_t __pte2cachemode_tbl[8]; ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \ (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \ (((cb) >> _PAGE_BIT_PWT) & 1)) +#define __cm_idx2pte(i) \ + ((((i) & 4) << (_PAGE_BIT_PAT - 2)) | \ + (((i) & 2) << (_PAGE_BIT_PCD - 1)) | \ + (((i) & 1) << _PAGE_BIT_PWT)) static inline unsigned long cachemode2protval(enum page_cache_mode pcm) { |