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| author | Len Brown | 2013-01-31 21:22:15 +0100 |
|---|---|---|
| committer | Len Brown | 2013-02-09 01:26:16 +0100 |
| commit | 679204183472af16e8e75d2b1479459ad19bc67c (patch) | |
| tree | 0508a4b33d9bfbb608c854da62da02224e0c1aa1 /arch/x86/include/uapi/asm/msr-index.h | |
| parent | tools/power turbostat: support Haswell (diff) | |
| download | kernel-qcow2-linux-679204183472af16e8e75d2b1479459ad19bc67c.tar.gz kernel-qcow2-linux-679204183472af16e8e75d2b1479459ad19bc67c.tar.xz kernel-qcow2-linux-679204183472af16e8e75d2b1479459ad19bc67c.zip | |
tools/power turbostat: decode MSR_IA32_POWER_CTL
When verbose is enabled, print the C1E-Enable
bit in MSR_IA32_POWER_CTL.
also delete some redundant tests on the verbose variable.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/x86/include/uapi/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 433a59fb1a74..7bdaf7c9b1e0 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -103,6 +103,8 @@ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) +#define MSR_IA32_POWER_CTL 0x000001fc + #define MSR_IA32_MC0_CTL 0x00000400 #define MSR_IA32_MC0_STATUS 0x00000401 #define MSR_IA32_MC0_ADDR 0x00000402 |