diff options
| author | Jacob Shin | 2013-04-19 23:34:28 +0200 |
|---|---|---|
| committer | Ingo Molnar | 2013-04-21 11:01:24 +0200 |
| commit | c43ca5091a374c1f6778bd7e4a39a5a10735a917 (patch) | |
| tree | f9bc7384913f2c173d871cd506f9fec521cfc458 /arch/x86/include/uapi/asm/msr-index.h | |
| parent | perf/x86/intel: Add Ivy Bridge-EP uncore support (diff) | |
| download | kernel-qcow2-linux-c43ca5091a374c1f6778bd7e4a39a5a10735a917.tar.gz kernel-qcow2-linux-c43ca5091a374c1f6778bd7e4a39a5a10735a917.tar.xz kernel-qcow2-linux-c43ca5091a374c1f6778bd7e4a39a5a10735a917.zip | |
perf/x86/amd: Add support for AMD NB and L2I "uncore" counters
Add support for AMD Family 15h [and above] northbridge
performance counters. MSRs 0xc0010240 ~ 0xc0010247 are shared
across all cores that share a common northbridge.
Add support for AMD Family 16h L2 performance counters. MSRs
0xc0010230 ~ 0xc0010237 are shared across all cores that share a
common L2 cache.
We do not enable counter overflow interrupts. Sampling mode and
per-thread events are not supported.
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
Cc: Stephane Eranian <eranian@google.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20130419213428.GA8229@jshin-Toonie
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/include/uapi/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index bf7bb68f43a8..b5757885d7a4 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -196,6 +196,10 @@ #define MSR_AMD64_IBSBRTARGET 0xc001103b #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ +/* Fam 16h MSRs */ +#define MSR_F16H_L2I_PERF_CTL 0xc0010230 +#define MSR_F16H_L2I_PERF_CTR 0xc0010231 + /* Fam 15h MSRs */ #define MSR_F15H_PERF_CTL 0xc0010200 #define MSR_F15H_PERF_CTR 0xc0010201 |