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| author | Kristen Carlson Accardi | 2012-11-21 14:22:43 +0100 |
|---|---|---|
| committer | Len Brown | 2013-04-18 01:23:26 +0200 |
| commit | ca58710f3ae585ed6203043cc6d4ffb805adeee4 (patch) | |
| tree | 9c35a136094b3d196937176c198d0a66cf88d06f /arch/x86/include/uapi/asm/msr-index.h | |
| parent | tools/power turbostat: additional Haswell CPU-id (diff) | |
| download | kernel-qcow2-linux-ca58710f3ae585ed6203043cc6d4ffb805adeee4.tar.gz kernel-qcow2-linux-ca58710f3ae585ed6203043cc6d4ffb805adeee4.tar.xz kernel-qcow2-linux-ca58710f3ae585ed6203043cc6d4ffb805adeee4.zip | |
tools/power turbostat: display C8, C9, C10 residency
Display residency in the new C-states, C8, C9, C10.
C8, C9, C10 are present on some:
"Fourth Generation Intel(R) Core(TM) Processors",
which are based on Intel(R) microarchitecture code name Haswell.
Signed-off-by: Kristen Carlson Accardi <kristen@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/x86/include/uapi/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 892ce40a7470..78e852545abb 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -118,6 +118,9 @@ #define MSR_CORE_C6_RESIDENCY 0x000003fd #define MSR_CORE_C7_RESIDENCY 0x000003fe #define MSR_PKG_C2_RESIDENCY 0x0000060d +#define MSR_PKG_C8_RESIDENCY 0x00000630 +#define MSR_PKG_C9_RESIDENCY 0x00000631 +#define MSR_PKG_C10_RESIDENCY 0x00000632 /* Run Time Average Power Limiting (RAPL) Interface */ |