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| author | Linus Torvalds | 2009-06-23 06:38:22 +0200 |
|---|---|---|
| committer | Linus Torvalds | 2009-06-23 06:38:22 +0200 |
| commit | 687d680985b1438360a9ba470ece8b57cd205c3b (patch) | |
| tree | ae253608531e5c3e823600974c610e722e7de759 /arch/x86/include | |
| parent | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/iee... (diff) | |
| parent | intel-iommu: Fix one last ia64 build problem in Pass Through Support (diff) | |
| download | kernel-qcow2-linux-687d680985b1438360a9ba470ece8b57cd205c3b.tar.gz kernel-qcow2-linux-687d680985b1438360a9ba470ece8b57cd205c3b.tar.xz kernel-qcow2-linux-687d680985b1438360a9ba470ece8b57cd205c3b.zip | |
Merge git://git.infradead.org/~dwmw2/iommu-2.6.31
* git://git.infradead.org/~dwmw2/iommu-2.6.31:
intel-iommu: Fix one last ia64 build problem in Pass Through Support
VT-d: support the device IOTLB
VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps
VT-d: add device IOTLB invalidation support
VT-d: parse ATSR in DMA Remapping Reporting Structure
PCI: handle Virtual Function ATS enabling
PCI: support the ATS capability
intel-iommu: dmar_set_interrupt return error value
intel-iommu: Tidy up iommu->gcmd handling
intel-iommu: Fix tiny theoretical race in write-buffer flush.
intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing.
intel-iommu: Clean up handling of "caching mode" vs. context flushing.
VT-d: fix invalid domain id for KVM context flush
Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support
Intel IOMMU Pass Through Support
Fix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/iommu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index af326a2975b5..fd6d21bbee6c 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -6,6 +6,7 @@ extern void no_iommu_init(void); extern struct dma_map_ops nommu_dma_ops; extern int force_iommu, no_iommu; extern int iommu_detected; +extern int iommu_pass_through; /* 10 seconds */ #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) |