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| author | Andi Kleen | 2009-07-09 00:31:44 +0200 |
|---|---|---|
| committer | H. Peter Anvin | 2009-07-10 03:39:47 +0200 |
| commit | a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54 (patch) | |
| tree | ac4adb869a19d3cb0f67516b667a1f60e5c3cfa9 /arch/x86/include | |
| parent | x86: mce: Move per bank data in a single datastructure (diff) | |
| download | kernel-qcow2-linux-a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54.tar.gz kernel-qcow2-linux-a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54.tar.xz kernel-qcow2-linux-a2d32bcbc008aa0f9c301a7c6f3494cb23e6af54.zip | |
x86: mce: macros to compute banks MSRs
Instead of open coded calculations for bank MSRs hide the indexing of higher
banks MCE register MSRs in new macros.
No semantic changes.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1692fb5050e3..3d1ce094586a 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -81,8 +81,15 @@ #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_MISC 0x00000403 +#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) +#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) +#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) +#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) + /* These are consecutive and not in the normal 4er MCE bank block */ #define MSR_IA32_MC0_CTL2 0x00000280 +#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) + #define CMCI_EN (1ULL << 30) #define CMCI_THRESHOLD_MASK 0xffffULL |