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| author | Naga Chumbalkar | 2011-07-12 07:59:07 +0200 |
|---|---|---|
| committer | H. Peter Anvin | 2011-07-12 23:33:49 +0200 |
| commit | 25970852280c9d5fb2de899769880d3e97332baa (patch) | |
| tree | 164c46e430637f790ed2e495155fd8fc724e47f5 /arch/x86/kernel/apic/apic.c | |
| parent | x86, ioapic: Also print Dest field (diff) | |
| download | kernel-qcow2-linux-25970852280c9d5fb2de899769880d3e97332baa.tar.gz kernel-qcow2-linux-25970852280c9d5fb2de899769880d3e97332baa.tar.xz kernel-qcow2-linux-25970852280c9d5fb2de899769880d3e97332baa.zip | |
x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
MSR, let's preserve it.
The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2
in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
Link: http://lkml.kernel.org/r/20110712055831.2498.78521.sendpatchset@nchumbalkar.americas.cpqcorp.net
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/apic/apic.c')
| -rw-r--r-- | arch/x86/kernel/apic/apic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index b9338b8cf420..f7b0c7a1dfaa 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1429,7 +1429,7 @@ void enable_x2apic(void) rdmsr(MSR_IA32_APICBASE, msr, msr2); if (!(msr & X2APIC_ENABLE)) { printk_once(KERN_INFO "Enabling x2apic\n"); - wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); + wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2); } } #endif /* CONFIG_X86_X2APIC */ |