diff options
| author | Andi Kleen | 2011-10-13 02:46:33 +0200 |
|---|---|---|
| committer | Ingo Molnar | 2011-10-14 13:16:35 +0200 |
| commit | 506ed6b53e00ba303ad778122f08e1fca7cf5efb (patch) | |
| tree | 264fa332aa060c396caa89d41cbb6f7c5e7f4d3f /arch/x86/kernel/cpu/intel.c | |
| parent | x86, microcode: Don't request microcode from userspace unnecessarily (diff) | |
| download | kernel-qcow2-linux-506ed6b53e00ba303ad778122f08e1fca7cf5efb.tar.gz kernel-qcow2-linux-506ed6b53e00ba303ad778122f08e1fca7cf5efb.tar.xz kernel-qcow2-linux-506ed6b53e00ba303ad778122f08e1fca7cf5efb.zip | |
x86, intel: Output microcode revision in /proc/cpuinfo
I got a request to make it easier to determine the microcode
update level on Intel CPUs. This patch adds a new "microcode"
field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks
together with the other CPUID model information.
I removed the respective code from the microcode update driver,
it just reads the field from cpu_data. Also when the microcode
is updated it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it
being optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index ed6086eedf1d..26627a3a7148 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -47,6 +47,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) (c->x86 == 0x6 && c->x86_model >= 0x0e)) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) { + unsigned lower_word; + + wrmsr(MSR_IA32_UCODE_REV, 0, 0); + /* Required by the SDM */ + sync_core(); + rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode); + } + /* * Atom erratum AAE44/AAF40/AAG38/AAH41: * |