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| author | Andi Kleen | 2013-06-18 02:36:47 +0200 |
|---|---|---|
| committer | Ingo Molnar | 2013-06-19 14:43:32 +0200 |
| commit | 130768b8c93cd8d21390a136ec8cef417153ca14 (patch) | |
| tree | 01900496205e221dd6ad855352e3b1df6d6be1c6 /arch/x86/kernel/cpu/perf_event.c | |
| parent | perf/x86/intel: Fix sparse warning (diff) | |
| download | kernel-qcow2-linux-130768b8c93cd8d21390a136ec8cef417153ca14.tar.gz kernel-qcow2-linux-130768b8c93cd8d21390a136ec8cef417153ca14.tar.xz kernel-qcow2-linux-130768b8c93cd8d21390a136ec8cef417153ca14.zip | |
perf/x86/intel: Add Haswell PEBS record support
Add support for the Haswell extended (fmt2) PEBS format.
It has a superset of the nhm (fmt1) PEBS fields, but has a
longer record so we need to adjust the code paths.
The main advantage is the new "EventingRip" support which
directly gives the instruction, not off-by-one instruction. So
with precise == 2 we use that directly and don't try to use LBRs
and walking basic blocks. This lowers the overhead of using
precise significantly.
Some other features are added in later patches.
Reviewed-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <ak@linux.jf.intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: http://lkml.kernel.org/r/1371515812-9646-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event.c')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index e52a9e577783..ab3395295224 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -403,7 +403,8 @@ int x86_pmu_hw_config(struct perf_event *event) * check that PEBS LBR correction does not conflict with * whatever the user is asking with attr->branch_sample_type */ - if (event->attr.precise_ip > 1) { + if (event->attr.precise_ip > 1 && + x86_pmu.intel_cap.pebs_format < 2) { u64 *br_type = &event->attr.branch_sample_type; if (has_branch_stack(event)) { |