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| author | Thomas Gleixner | 2015-05-19 02:00:50 +0200 |
|---|---|---|
| committer | Ingo Molnar | 2015-05-27 09:17:38 +0200 |
| commit | f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0 (patch) | |
| tree | 4f67700eba0d5fab74cfa5b07b4e988208afb06d /arch/x86/kernel/cpu/perf_event_intel_cqm.c | |
| parent | Merge branch 'perf/urgent' into perf/core, before applying dependent patches (diff) | |
| download | kernel-qcow2-linux-f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0.tar.gz kernel-qcow2-linux-f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0.tar.xz kernel-qcow2-linux-f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0.zip | |
perf/x86/intel/cqm: Document PQR MSR abuse
The CQM code acts like it owns the PQR MSR completely. That's not true
because only the lower 10 bits are used for CQM. The upper 32 bits are
used for the 'CLass Of Service ID' (CLOSID). Document the abuse. Will be
fixed in a later patch.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Matt Fleming <matt.fleming@intel.com>
Cc: Kanaka Juvva <kanaka.d.juvva@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: Will Auld <will.auld@intel.com>
Link: http://lkml.kernel.org/r/20150518235149.823214798@linutronix.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event_intel_cqm.c')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel_cqm.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c index e4d1b8b738fa..572582e2143e 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c +++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c @@ -978,7 +978,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode) WARN_ON_ONCE(state->rmid); state->rmid = rmid; - wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid); + /* + * This is actually wrong, as the upper 32 bit MSR contain the + * closid which is used for configuring the Cache Allocation + * Technology component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0); raw_spin_unlock_irqrestore(&state->lock, flags); } @@ -998,7 +1003,13 @@ static void intel_cqm_event_stop(struct perf_event *event, int mode) if (!--state->cnt) { state->rmid = 0; - wrmsrl(MSR_IA32_PQR_ASSOC, 0); + /* + * This is actually wrong, as the upper 32 bit of the + * MSR contain the closid which is used for + * configuring the Cache Allocation Technology + * component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, 0, 0); } else { WARN_ON_ONCE(!state->rmid); } |